Semiconductor power devices, in terms of blocking voltage in design, should provide characteristics of minimum conduction resistance, lower reverse leakage current and faster switching speed to reduce conduction loss and switching loss during operation. Silicon carbide (SiC) has characteristics of a wide energy bandgap (for instance, energy bandgap of 4H—SiC is 3.26 eV, compared to 1.1 eV of silicon), a higher critical field of dielectric breakdown (2.2 MV/cm) and a higher thermal conduction coefficient (4.9 W/cm-K), hence is deemed an excellent material for making power switching devices. Silicon carbide is also the only compound semiconductor can form thermally grown oxides, hence is suitable for manufacturing MOS controlled switches such as MOSFET (metal oxide semiconductor field effect transistor) and IGBT (insulated gate bipolar transistor).
For example, the U.S. Pat. No. 8,994,118 B2 discloses a conventional SiC MOSFET. The above disclosure mainly includes a semiconductor substrate layer of a first conductivity type, a drift layer of the first conductivity type, a first well region of a second conductivity type, a second well region of the second conductivity type, a first source region of the first conductivity type, a second source region of the first conductivity type, a first gate dielectric layer, a gate electrode, an interlayer dielectric material, and a source ohmic contact. The drift layer is on the substrate layer. The first well region is in a central portion of the drift layer. The second well region is in the central portion of the drift layer and is spaced from the first well region. The first source region is in the first well region. The second source region is in the second well region. The first gate dielectric layer is on the drift layer and is in contact with the first source region and the second source region. The gate electrode is on the first gate dielectric layer, and includes a lower surface on the first gate dielectric layer, an upper surface opposite the lower surface and sidewalls. The interlayer dielectric material is on the upper surface and is adjacent the sidewalls of the gate electrode. The source ohmic contact is in the first source region and the second source region.
The oxidation rate of SiC depends on the conductivity types, doping concentrations as well as polytypes of SiC. In a conventional SiC MOSFET, as the source region is generally formed on a surface of a drift layer with a high concentration of n-type doping (with phosphorus as a dopant). While the gate oxide layer is grown, the high-concentration n-type doped region has a faster oxidation rate than that of a p-type well, hence resulting in an uneven thickness of the gate oxide layer. Further, during the process of forming high doping concentration source region, a part of lattices of SiC may be damaged due to collisions with implanted ions to transform into amorphous structures. These amorphous structures may become other polytypes when the lattices are restored in a subsequent activation annealing process. For example, assuming that the polytype of the original drift layer is 4H, the polytype of a part of the drift layer may become 3C after the annealing process. Thus a rough oxide/SiC interface will be formed after the growth of gate oxide because of different oxidation rates of 4H and 3C polytypes. As a result, a high electric field may be crowded around some localized points of gate oxide, and poses reliability concerns.
In addition, during the thermal oxidation of SiC, the unreacted carbon will remain at the interface and inside of oxide as defects in the form of silicon vacancies, carbon clusters and carbon interstitials, and create energy states in the band gap. These defect states will become acceptor-like traps or donor-like traps at the interface. In general, SiC MOSFET are n-channel MOSFETs. When inversion channel is formed on the p-well, the electrons will be captured by acceptor-like traps near the conduction band, and the density of electrons available for conducting electric current will be reduced. In the meantime the acceptor-like traps filled with electrons will become negatively charged, and cause significant Coulomb scattering of electrons. The reduced electron density and significant Coulomb scattering explain the very low channel mobility and high conduction resistance of SiC MOSFET. Approaches of improving channel mobility and conduction resistance include passivation of the interface traps by post-oxidation annealing with nitric oxide (NO), nitrous oxide (N2O) or POCl3. Non-patent references can be found as follows:    [1] S. Salemi, N. Goldsman, D. P. Eittsserry, A. Akturk, A. Lelis, J. Appl. Phys. 113, 053703, 2013;    [2] D. Okamoto, H. Yano, Y. Oshiro, T. Hatayama, Y. Uraoka and T. Fuyuki, Materials Science Forum Vols. 645-648, 2010 pp 515-518;    [3] Y K. Sharma, A. C. Ahyi, T. Issacs-Smith, X. Shen, S. T. Pantelides, X. Zhu, L. C. Feldman, J. Rozen, J. R. Williams, Solid-State Electronics 68 (2012) 103-107.    [4] John Rozen, Ayayi C. Ahyi, Xingguang Zhu, John R. Williams, and Leonard C. Feldman, IEEE Transactions on Electron Devices, Vol. 58, No. 11, November 2011, pp. 3808-3811.    [5] John Rozen, Xingguang Zhu, A. C. Ahyi, J. R. Williams and L. C. Feldman, Materials Science Forum Vols. 645-648 (2010) pp 693-696.    [6] Constantin Bulucea and Daniel Kerr, Solid-State Electronics Vol. 41, No. 9, pp. 1345-1354, 1997.    [7] S. Harada, M. Kato, M. Okamoto, T. Yatsuo, K. Fukuda, K. Arai, Proceedings of the 18th International Symposium on Power Semiconductor Devices & IC's Jun. 4-8, 2006 Naples, Italy.    [8] Shinsuke Harada, Makoto Kato, Mitsuo Okamoto, Tsutomu Yatsuo, Kenji Fukuda and Kazuo Arai, Materials Science Forum Vols. 527-529 (2006) pp 1281-1284.    [9] William E. Wagner, III and Marvin H. White, IEEE Transactions on Electron Devices, Vol. 47, No. 11, November 2000, Pp. 2214-2219.    [10] Tsunenobu Kimoto, Japanese Journal of Applied Physics 54, 040103 (2015).
However, the current approaches of reducing on-resistance usually face the trade-off of lowered MOSFET threshold voltage. A low threshold voltage increases the risk of falsely turn-on during operation of devices